1. Technical Field
The present invention described herein relates to a non-volatile semiconductor memory circuit and, more particularly, to a non-volatile semiconductor memory circuit for generating a write voltage.
2. Related Art
Generally, a phase change random access memory (PRAM) tends to be researched and developed to be adopted to various semiconductor systems and semiconductor memory devices due to a characteristic in that it is common that the PRAM can randomly access data although the PRAM is a non-volatile memory.
A unit cell of the PRAM often times includes a diode, for example, one switching element connected to a word line and one variable resistor GST coupled to a bit line. The PRAM controls the reversible phase change of the variable resistor GST of the PRAM using electric pulse to store data in a memory cell. For example, a pulse signal of high voltage is applied for a predetermined time why the state of the variable resistor GST be changed during a write (or program) operation in the PRAM. At this time, in order to apply a high write voltage, voltage pump circuits are provided.
The PRAM commonly includes a plurality of voltage pump circuits to control the number of pumps driven in accordance with a data input and output mode to vary. Therefore, the PRAM requires a circuit for selecting the data input and output mode. In addition, a voltage in a no less than uniform level lower than the high voltage required for actually performing a write operation in a standby state where write and read operations are not performed is maintained so that the high voltage can be rapidly provided in a write mode. Therefore, a voltage pump circuit for the standby state is also required.
Therefore, since the PRAM needs the circuit for selecting the data input and output mode and separate controllers in the standby state and an active state (where the pumps are required to be driven), a large footprint is needed and the structure of the circuits is complicated.